This paper presents a 64-channel time-domain multiplexed (TDM) neural recording IC that achieves a high total input impedance (T-Z) for direct interfacing with a time-multiplexed microelectrode array (MEA). Unlike conventional IC-side multiplexing implementations, the proposed system performs multiplexing at the electrode side, creating a shared external parasitic path across channels and allows the dual positive feedback loop (DPFL) to use shared feedback capacitors and a single calibration code. The DPFL cancels both internal and external parasitics, thereby boosting T-Z. Thus, the proposed scheme eliminates parasitic mismatch and improves scalability and T-Z than prior works. Fabricated in a 180 nm CMOS process, the system implements 8 to 1 multiplexing per analog front end, achieves 3.3 GΩ T-Z at 10 Hz with 3 pF added external capacitance, and demonstrates saline-based spike recording with 6.66 $μ$V input referred noise over 1 Hz to 10 kHz, while consuming 8.87 $μ$W per channel and 0.0619 mm per channel.

TThis article presents the first co-designed MRI imaging and magnetic positioning system for real-time dynamic motion compensation, achieving sub-millimeter tracking accuracy while preserving diagnostic image quality. The core innovation lies in a system-level co-design of an MRI imaging system and a magnetic localization system, featuring a customized receiver IC for processing magnetic signals coupled by the frontend RF coils, enabling artifact-free MRI imaging in dynamic scenarios. This integration enables a median positioning accuracy of 0.66 mm across a 40×40×50 cm field-of-view with a total power consumption of 997 $μ$W. The key innovations include: 1) a time-division multiplexing scheme to enable signal detection from different coils while achieving spectral isolation between 1.4 MHz positioning signals and MRI Larmor frequencies through FPGA-synchronized blanking; 2) a dynamic calibration algorithm fusing magnetic tracking data with multi-frame MRI imaging, reducing spatial blur radius by 40% via weighted averaging; 3) an MRI-optimized Levenberg-Marquardt algorithm incorporating dynamic magnetic beacon weighting and spatial constraints, improving localization accuracy by 53% versus conventional algorithm. The system utilizes planar magnetic beacons with a dimension of 3×3 cm, reducing spatial occupancy compared to prior designs. This work bridges critical gaps between high-precision tracking and artifact-free MRI, enabling real-time imaging of non-autonomous motion and respiratory motion compensation, representing a paradigm shift for MRI-guided interventions.

Surgical tumor resection aims to remove all cancer cells in the tumor margin and at centimeter-scale depths below the tissue surface. During surgery, microscopic clusters of disease are intraoperatively difficult to visualize and are often left behind, significantly increasing the risk of cancer recurrence. Radioguided surgery (RGS) has shown the ability to selectively tag cancer cells with gamma (γ) photon emitting radioisotopes to identify them, but require a mm-scale γ photon spectrometer to localize the position of these cells in the tissue margin (i.e., a function of incident γ photon energy) with high specificity. Here we present a 9.9 mm integrated circuit (IC)-based γ spectrometer implemented in 180 nm CMOS, to enable the measurement of single γ photons and their incident energy with sub-keV energy resolution. We use small 2 × 2 μm reverse-biased diodes that have low depletion region capacitance, and therefore produce millivolt-scale voltage signals in response to the small charge generated by incident γ photons. A low-power energy spectrometry method is implemented by measuring the decay time it takes for the generated voltage signal to settle back to DC after a γ detection event, instead of measuring the voltage drop directly. This spectrometry method is implemented in three different pixel architectures that allow for configurable pixel sensitivity, energy-resolution, and energy dynamic range based on the widely heterogenous surgical and patient presentation in RGS. The spectrometer was tested with three common γ-emitting radioisotopes (Cu, Ba, Lu), and is able to resolve activities down to 1 μCi with sub-keV energy resolution and 1.315 MeV energy dynamic range, using 5-minute acquisitions.

Three-dimensional (3D) cell culture is gaining attention for its ability to better mimic tissue environments in vitro, enhancing drug screening efficiency. Tracking biological dynamics in such a setup requires advanced monitoring technologies. This paper presents a miniature magnetic resonance imaging (MRI) platform tailored for imaging 3D cell-culture morphology within a microliter-volume microwell, enabling real-time and on-site visualization of biological dynamics. The system utilizes an MRI application-specific integrated circuit for excitation and detection of the nuclear magnetic resonance (NMR) signal. To cope with the small-volume sensing, the platform features a customized frontend probe, which includes a miniaturized saddle coil and a PDMS-molded sample well for in-situ microliter sample containment and detection. Our proof-of-concept measurements on samples demonstrate an MRI image resolution of 90×128×88 $\rm \mu m$, along with continuous, multi-perspective (transverse and longitudinal) imaging of 3D cultures, including spheroid slice visualization. These results highlight the system's applicability and potential for future biological analysis and drug screening, offering researchers a valuable tool for advancing in vitro studies.

Brain-machine interface (BMI) technology enables the human brain to communicate directly with machines. This work presents a neural signal processor for real-time BMI, supporting translation from user's speech attempt to sentences. By employing speech attempt detection, the energy consumption is reduced by 46% and the number of channels for speech attempt detection can be decreased from 128 to 16. The proposed weight encoding, which leverages both sparse encoding and mixed-precision arithmetic, reduces the off-chip memory size of the neural network by 80%. Computation reordering decreases the processing latency by 55%. For the partial sum caching technique, the number of neural network operations is reduced by 25%. The processing element (PE) array in the neural network engine exploits both input and weight sparsity to lower the processing latency by 95%. By using the proposed mixed-precision multiplier in the PE array, the area is reduced by 27% compared with the PE array with the full precision. In the beam search engine, the proposed approximate top-k selection architecture exhibits 16× fewer comparators. The neural signal processor achieves speech decoding with a phone error rate of 16.6% and a word error rate of 23.5%. Fabricated in 40-nm CMOS, the chip achieves the maximum communication rate of 200 words/min, which is 16.7-to-42.6× faster than the state-of-the-art designs. This work is able to decode up to 125,000 words, which is not achievable by prior works that can only decode up to 31 characters.

In this work, a biphasic and bipolar current-controlled stimulator with high loading adaptability is proposed. The stimulator consisted of an on-chip high voltage generator, output driver and an 8-bit current DAC (Digital-to-Analog Converter), can constantly provide the required stimulus currents ranging from 0.1mA to a maximum of 20mA, as the loading impedance varied within 0.5kΩ - 5kΩ. With a nearly 12 V output voltage, the overstress and reliability issues of the circuits are thoroughly considered and carefully addressed in this work. To achieve high loading impedance adaptability, this paper proposes a novel PAM (Pulse Amplitude Modulation) loop control architecture to drive the charge pump (CP), which provides a significantly higher output dynamic range compared to conventional methods such as PFM (Pulse Frequency Modulation) and PSM (Pulse Skip Modulation). In addition, to further improve the Power Conversion Efficiency (PCE) of the high voltage generator, a new technique, PAM-based Dual-Domain Voltage Scaling (PAM-DDVS), is proposed to minimize unnecessary energy consumption while achieving high adaptive range. The fully-integrated stimulus chip with 2 output channels is fabricated in TSMC 0.18μm 1.8V/3.3V process, and occupies a core die area of approximately 1.6 mm. Imitation tests are conducted to validate the functionality of the stimulus chip.

Minimally invasive wireless implants distributed in the nervous system can transfer various neural signals to an external device, offering an effective hardware tool for neuro-disorder monitoring. Battery-free wireless techniques based on wireless power transfer (WPT) have been adopted to minimize the neural implants, but the effective reading ranges of most conventional works are not long enough to access deep-tissue nerves. The existing ultrasonic coupling and binary-driven passive body-channel-communication (BCC) techniques extended the reading range but suffered from a low data rate and a high energy in wireless communication. In this work, we demonstrate a battery-free wireless neural implant based on the proposed pulse-width-modulation (PWM) passive-BCC technique, which improves the data rate and further reduces the energy per bit. The proposed technique is implemented in a neural-recording chip fabricated by a 65nm CMOS process. Measured results show that the proposed wireless neural implant achieves a battery-free reading range of 6cm, with an energy efficiency of 36.2pJ/bit. In-vivo experiment is performed in a Sprague-Dawley rat to record the neural signals wirelessly in a battery-free way.

The liquid state machine (LSM), a reservoir computing variant of spiking neural networks (SNNs), has been widely adopted for its low training complexity. In this work, we propose C2-LSM, a neuromorphic processor designed through algorithm-hardware co-design to achieve high accuracy across diverse tasks. At the algorithm level, inspired by the "small-world" structure of the biological brain, we introduce a novel reservoir layer in which neurons are interconnected using a cubecluster topology. For hardware implementation, the customized C2-LSM processor supports runtime configurability of reservoir size and connection sparsity, enabling high classification accuracy across a range of spatiotemporal tasks. Additionally, a Network-on-Chip (NoC) with a Storm routing algorithm is developed to improve the spike event transmission throughput among reservoir neurons. C2-LSM is implemented on an AMD Virtex UltraScale+ VCU129 FPGA running at 250 MHz. With on-chip learning, it achieves accuracies of 98.02%, 94.26%, and 93.00% on MNIST, N-MNIST, and FSDD datasets, respectively, outperforming recently benchmarked LSM neuromorphic processors across all three tasks. For the MNIST task, it achieves an inference speed of 1155 FPS and a learning speed of 1154 FPS, along with a high power efficiency of 103 GSOPS/W.

This review provides a comprehensive overview of techniques for mitigating common-mode interference (CMI) in biopotential analog front-ends (AFEs). The mechanisms of CMI generation in various biopotential measurement scenarios, including neurostimulation and two-electrode ECG, are modeled electrically. The impact of CMI on signal quality is analyzed from both small-signal and large-signal views, highlighting the scenario-dependent nature of the CMI issue. Techniques for improving the common-mode rejection ratio (CMRR) are introduced to suppress CMI in small-signal conditions. The concept of total CMRR (TCMRR), which incorporates the effect of asymmetric contact impedance, is reviewed, and corresponding design strategies for maximizing TCMRR are analyzed. In the large-signal view, CMI-induced distortion and approaches for enhancing tolerance CMI are discussed, addressing both sub-supply and over-supply CMI scenarios. By analyzing mitigation techniques across different measurement contexts, this review offers practical design insights to guide future biopotential AFE designers in selecting the most appropriate solutions.

Surface-bound electrochemical aptamer-based (E-AB) sensors are a promising approach for continuous in-vivo and in-vitro biomolecular monitoring because they offer high selectivity, sensitivity, and real-time detection. However, accurately co-simulating E-AB sensors with readout circuits remains challenging due to the redox reporter's position-dependent electron-transfer kinetics and the electrical double layer's (EDL) complex behavior at the electrode-electrolyte interface. Here, we present a compact, SPICE-compatible electrochemical cell model that combines a Verilog-A implementation of the Marcus-Hush-based electron-transfer (ET) kinetics with a fractional-order RC-ladder representation of the EDL's non-ideal capacitance. The conventional Butler-Volmer model is replaced by Marcus-Hush kinetics, which features bounded and quantum mechanically derived ET rate constants, improving not only the model's physical interpretability but also numerical stability in circuit simulations. The model was validated with two E-AB sensors using square-wave voltammetry (SWV) across a range of excitation frequencies and target concentrations to confirm that the simulated transient currents accurately capture ET kinetics, thermodynamics, and the Langmuir isotherm's concentration response. When co-simulated with a transimpedance amplifier constructed with the TI OPA4354, the model produced electronic noise spectra that more closely matched experimental data, when compared with spectra simulated using the simplified Randles circuit model. These results demonstrate that the proposed model provides a physically grounded framework for simulating surface-bound redox-based electrochemical biosensors and enables accurate co-simulation with readout circuits.

This paper presents an A-mode ultrasound scanner application-specific integrated circuit (ASIC) for arterial distension monitoring. The ASIC operates with a single-element ultrasound probe, identifying a target artery through echo pattern recognition and reconstructing an arterial diameter waveform. A 1-D convolutional neural network (CNN) is employed to ensure accurate probe positioning by recognizing characteristic arterial wall echo patterns. Additionally, gradient-weighted class activation mapping (Grad-CAM) is utilized to adaptively localize arterial wall regions, facilitating the measurement of arterial diameter in each A-mode frame. The ASIC includes a high-voltage pulser, a transmit/receive (T/R) switch, an analog front-end, and a synthesized digital circuit for post processing. The ASIC has been fabricated in a 180-nm BCD process, occupying an active area of 2.8 mm with a power consumption of 1.65 mW. The fabricated ASIC was evaluated for CNN inference performance and accuracy of arterial distension estimation, achieving a CNN inference accuracy of 95% and a Pearson correlation coefficient (r) of 0.895. Compared to prior ultrasound scanners, the proposed ASIC achieves a high inference accuracy in echo pattern recognition and an efficient implementation of mixed-signal architecture, demonstrating high feasibility of a small footprint ultrasound module for physiological instrumentation.

Epilepsy affects over 50 million people world-wide, posing a significant clinical challenge, particularly for patients unresponsive to conventional treatments. Advances in neural implants with on-device algorithms are revolutionizing epilepsy management by enabling precise, real-time seizure detection and reducing the technical and financial burden of data transmission. The current trend advances towards the integration of a larger number of electrodes in neural implants, enhancing spatial resolution and broadening brain coverage. Consequently, the increasing data demands necessitate highly efficient processing to minimize transmission bandwidth and power consumption, ensuring the long-term viability of implantable systems. This work presents a novel approach using time-series segmentation (TSS) to extract labeled information from raw recordings. The algorithm explores multiple outlier detection methods with a heuristic low-complexity event classifier, and employs a multichannel consensus strategy to improve detection accuracy through multichannel agreement. This system enables high-performance seizure detection and segments local field potentials (LFP) into clinically relevant labels for interpretation and post-processing. Tested on microelectrode array (MEA) recordings from mouse hippocampus-cortex slices treated with 4-aminopyridine, the system demonstrated robust reliability. Implemented on a Pynq-Z2 board with a Zynq 7020 System-on-Chip, the algorithm requires minimal calibration, achieving 95% accuracy, 94% sensitivity, and a 0.03% FPR with a low power consumption of 128 mW for the best-performing outlier detector. By demonstrating the application of TSS to implantable device algorithms for on-device processing, this work advances towards more effective, personalized epilepsy treatments.

Neuroprostheses capable of providing Somatotopic Sensory Feedback (SSF) enables the restoration of tactile sensations in amputees, thereby enhancing prosthesis embodiment, object manipulation, balance and walking stability. Transcutaneous Electrical Nerve Stimulation (TENS) represents a primary noninvasive technique for eliciting somatotopic sensations. Devices commonly used to evaluate the effectiveness of TENS stimulation are often bulky and main powered. However, current portable TENS devices frequently fall short of key functional requirements, particularly in terms of stimulation parameter ranges that are insufficient to reliably evoke somatotopic sensations in either upper and lower limb applications. Moreover, they typically do not support real-time independent channels programming and wireless communication. This work introduces a compact, wearable stimulator, including its external casing, with a total weight of 64 g and dimensions of 70 % 40 % 35 mm, designed to deliver SSF in both upper and lower limb applications. The device was validated through bench testing and human trials involving 20 healthy participants, by comparing the intensity, qualitative characteristics, and referred area of the elicited sensations with those produced by a benchmark. The stimulator reliably delivered the required parameters on a skin-like capacitive-resistive load and elicited somatotopic sensations consistent with the benchmark device and prior somatotopic feedback studies. The proposed stimulator provides non-invasive somatotopic sensory feedback for both upper and lower limbs. Its portability and modular design address key limitations of current commercial and research-grade TENS systems, enabling future studies on the functional benefits of sensory feedback in prosthetic control.

In ECG classification applications, binarized convolutional neural networks (bCNNs) show great potential to achieve extremely low power consumption through 1-bit quantization. Existing bCNN approaches typically extract spatial features from the full ECG image without leveraging its sparsity, thereby introducing unnecessary computations and hardware resources. Meanwhile, inter-patient variability of ECG features degrades the classification performance due to accuracy loss caused by the binarization operation. To address these challenges, this paper proposes an energy-efficient ECG classifier based on a bCNN with on-chip learning. A patch-by-patch computation approach is used to reduce both power consumption and memory usage. Instead of processing the entire image, the ECG image is divided into small patches, and only the patches containing valid data are involved in feature extraction. An on-chip learning method is employed to improve classification accuracy among patients by updating the model weights using both the acquired bCNN features and the R-peak interval data. In addition, a reconfigurable convolutional processing element array and a base-2 softmax structure are designed to further reduce the hardware resources. The proposed classifier is verified on an FPGA, achieving a classification accuracy of 97.55% and a specificity of 89.15%. Synthesized using a 55 nm CMOS process, the ECG classifier occupies an area of 0.43 mm. With a supply voltage of 1.2 V, the classifier consumes an average energy of 0.12 $μ$J per classification and 0.09 $μ$J per on-chip learning, making it suitable for wearable ECG classification application.

We present a 192-channel 1D convolutional neural network (1D CNN) based neural feature extractor for Brain-Machine Interfaces (BMI) that achieves state-of-the-art decoding stability at 1.8 $μ$W and 12801 $μ$m per channel in 65nm CMOS technology. Our device is a fully configurable, scalable, area and power efficient solution that supports models with 2-8 feature layers and a total kernel length of up to 256. This architecture reduces caching requirements by 5× over conventional computation schemes. Channels and layers are individually power-switchable to further optimize power efficiency for a given neural application. We introduce an on-chip model, FENet-66, that achieves the highest cross-validated decoding performance compared to all previously reported feature sets. We show that this model maintains superior stability over time using recorded data from tetraplegic human participants with spinal cord injury. Our features have 18% higher overall average cross-validated R2 decoding performance compared to Spiking Band Power (SBP), with 28% better performance during the 4th year. Our proposed architecture can also extract mean wavelet power features at low power and latency. We show that custom 1D-CNN kernels achieve 10% better performance compared to wavelet features while compressing the neural data stream by 38×. The models and hardware were validated in real time with a human subject in online closed-loop center-out cursor control experiments with micro-electrode arrays that were implanted for 6 years. Decoders using features generated with this work substantially improve the viability of longterm neural implants compared to other feature extraction methods currently present in low power BMI hardware.

This paper presents a field-programmable gate array (FPGA) based medical image processing framework using a hardware-software co-design approach for biomedical tasks such as Malaria and Pneumonia detection. The design is implemented on the AMD-Xilinx UltraScale+ MPSoC (ZCU104) FPGA, focusing on optimizing data movement between the Processing System (PS) and Programmable Logic (PL) through a customized high-level synthesis (HLS) process. Depth-wise convolution is employed to reduce computational complexity, while layer fusion is applied to optimize layer-wise execution, and custom cache is integrated to improve memory access efficiency. The accelerated architecture is integrated with AXI interconnects and tested using the PYNQ overlay process. The experimental results demonstrate that the proposed accelerator achieves a throughput of 298.22 FPS and 205.87 FPS for the detection of malaria and pneumonia, respectively. The proposed design significantly improves energy efficiency, consuming 14.62 mJ/img for the detection of malaria and 23.89 mJ/img for the detection of pneumonia. Compared to alternative hardware platforms like Raspberry Pi with Coral TPU, the FPGA-based implementation offers superior performance, achieving 8.3× higher throughput and 4.3× better energy efficiency, making it well-suited for real-time medical image processing applications.

In [1], a critical labeling error was identified in Fig. 21, where the x-axis was incorrectly labeled "-50 ms to 50 ms" instead of the correct range "0 s to 5 s" (reflecting the actual ECG data duration). This discrepancy resulted from unintentional reuse of a plotting template and insufficient validation during proofing. While the underlying ECG waveform data remains accurate, the mislabeled scale misrepresents the signal's temporal characteristics. The Fig. 21 should be corrected as follows.

Magnetic resonance imaging (MRI) exhibits rich and clinically useful endogenous contrast mechanisms, which can differentiate soft tissues and are sensitive to flow, diffusion, magnetic susceptibility, blood oxygenation level, and more. However, MRI sensitivity is ultimately constrained by Nuclear Magnetic Resonance (NMR) physics, and its spatiotemporal resolution is limited by SNR and spatial encoding. On the other hand, miniaturized implantable sensors offer highly localized physiological information, yet communication and localization can be challenging when multiple implants are present. This paper introduces the MRDust, an active "contrast agent" that integrates active sensor implants with MRI, enabling the direct encoding of highly localized physiological data into MR images to augment the anatomical images. MRDust employs a micrometer-scale on-chip coil to actively modulate the local magnetic field, enabling MR signal amplitude and phase modulation for digital data transmission. Since MRI inherently captures the anatomical tissue structure, this method has the potential to enable simultaneous data communication, localization, and image registration with multiple implants. This paper presents the underlying physical principles, design tradeoffs, and design methodology for this approach. To validate the concept, a 900 × 990 µm chip was designed using TSMC 28 nm technology, with an on-chip coil measuring 630 µm in diameter. The chip was tested with custom hardware in an MR750W GE3T MRI scanner. Successful voxel amplitude modulation is demonstrated with Spin-Echo Echo-Planar-Imaging (SE-EPI) sequence, achieving a contrast-to-noise ratio (CNR) of 25.58 with a power consumption of 130 µW.

A wireless application-specific integrated circuit (ASIC), operating with the MagSonic modality using one magnetoelectric (ME) transducer, is presented for neural stimulation and recording. The ASIC integrates a bridge circuit that forms both power management and data transmitter with voltage doubling, rectification, regulation, and over voltage protection, a biphasic AC stimulator with high voltage tolerance and direct external control simplifying downlink complexities and on-chip processing overhead, an active charge balancing circuit adjusting the duration of second stimulation phase, and a continuous neural recording and uplink communication. The prototype MagSonic ASIC was fabricated in a 180 nm standard CMOS process (2×1.75 mm total area) and requires only one ME transducer and an external storage capacitor to operate. In measurements, a bar shaped millimeter-scale ME transducer (5.1×2.29×1.69 mm) with length mode operation at 330 kHz was used to power the ASIC, achieving up to 8.1 mW of received power at 40 mm depth. The biphasic AC stimulator occupying only 0.027 mm of active chip area provided 6.6 V (2×V) tolerance (using 3.3 V transistors) with residual electrode voltage of < 50 mV. The amplified signals were converted into time using an analog-to-time converter and transmitted at a data rate of 186.2 kbps (< 10 BER) using the ME transducer's thickness mode frequency (1.66 MHz). Animal experiment results demonstrate the feasibility of ASIC's direct AC stimulation.

Brain-computer interfaces rely on precise decoding of neural signals, where spike sorting is a critical step to extract individual neuronal activities from complex neural data. This works presents a spiking neural network (SNN) framework for efficient spike sorting, named SIFT-RSNN. In the SIFT-RSNN, raw neural signals are encoded into spike trains using a threshold-based temporal encoding strategy, then a sparse-integrated filtering module refines misfiring spikes, enhancing data sparsity for pattern learning. The RSNN module with a membrane shortcut structure ensures efficient feature transfer and improves generalization performance of the overall system. The SIFT-RSNN achieves an accuracy of 96.2% and 99.6% on the Difficult1 and Difficult2 subset of Leicester dataset, surpassing state-of-the-art methods. Also, we conducted it on a compute-in-memory platform with 8k memristor cells utilizing quantization-free mapping method and propose two algorithm-hardware co-optimization strategies to mitigate non-ideal hardware effects: weight outlier pre-constraint (WOP) and noise adaptation training (NAT). After optimization, our algorithm continues to outperform existing spike sorting methods, achieving accuracies of 94.2% and 99.7%, while also demonstrating improved robustness. The memristor platform only exhibits a 2% and 1.5% accuracy drop compared to software results on the two difficult subsets. Additionally, it achieves 3.52 μJ energy consumption and 0.5 ms latency per inference. This work offers promising solutions for brain-computer interfaces systems and neural prosthesis applications in the future.

This paper presents a fully-integrated single-input dual-output power management unit operating both in voltage/ current modes for powering mm-scale wireless neural implants. The chip operates in voltage mode most of the time, using an active full-wave rectifier to regulate a low-voltage, high-load output with high power efficiency and low output ripple (<32 mV). It switches to current mode rectification when generating a high-voltage, low-load output. This dual-mode operation allows for flexible power distribution and configurable voltage ratios between the two outputs. The selected 40.68 MHz operating frequency reduces the required capacitances for input impedance matching and output filtering, enabling on-chip integration; the only external component is the receiver coil. A novel resonance breakup switch compatible with full-wave rectification ensures a smooth cold start-up of the chip without any external voltage supply. The chip was fabricated using 40-nm CMOS technology with an active area of 1.18 mmand was tested in a wireless power link. Measurement results demonstrate that the chip can simultaneously regulate two outputs, $V_{LV} = \text{1 V}$ and $V_{HV} = \text{2 V}$, with a tested maximum output power of 10 mW and 32.6 μW on $V_{LV}$ and $V_{HV}$ , respectively. At the optimal output power condition $(P_{LV} = 4.4 \sim 6.7\, \text{mW})$, the system achieves a peak power conversion efficiency of 85.87% and a peak end-to-end efficiency of 17.32% when regulating $V_{LV}$. The end-to-end efficiency drops by only 2.38% when regulating both outputs with $R_{LV} = 225 \Omega$ and $R_{HV} = 400 \,\text{k}\Omega$.