This brief presents an on-chip digital intensive frequency-locked loop (DFLL)-based wakeup timer with a time-domain temperature compensation featuring a embedded temperature sensor. The proposed compensation exploits the deterministic temperature characteristics of two complementary resistors to stabilize the timer's operating frequency across the temperature by modulating the activation time window of the two resistors. As a result, it achieves a fine trimming step (± 1 ppm), allowing a small frequency error after trimming (<± 20 ppm). By reusing the DFLL structure, instead of employing a dedicated sensor, the temperature sensing operates in the background with negligible power (2 %) and hardware overhead (< 1 %). The chip is fabricated in 40 nm CMOS, resulting in 0.9 pJ/cycle energy efficiency while achieving 8 ppm/ºC from -40ºC to 80ºC.

Synchronous activities among neurons in the brain generate emergent network oscillations such as the hippocampal Sharp-wave ripples (SPWRs) that facilitate information processing during memory formation. However, how neurons and circuits are functionally organized to generate oscillations remains unresolved. Biophysical models of neuronal networks can shed light on how thousands of neurons interact in intricate circuits to generate such emergent SPWR network events. Here we developed a large-scale biophysically realistic neural network model of CA1 hippocampus with functionally organized circuit modules containing distinct types of neurons. Model simulations reproduced synaptic, cellular and network aspects of physiological SPWRs. The model provided insights into the role of neuronal types and their microcircuit motifs in generating SPWRs in the CA1 region. The model also suggests experimentally testable predictions including the role of specific neuron types in the genesis of hippocampal SPWRs.

Multielectrode arrays are used broadly for neural recording, both and for cultured neurons. In most cases, recording sites are passive electrodes wired to external read-out circuitry, and the number of wires is at least equal to the number of recording sites. We present an approach to break the conventional N-wire, N-electrode array architecture using graphene active electrodes, which allow signal upconversion at the recording site and sharing of each interface wire among multiple active electrodes using frequency-division multiplexing (FDM). The presented work includes the design and implementation of a frequency modulation and readout architecture using graphene FET electrodes, a custom integrated circuit (IC) analog front-end (AFE), and digital demodulation. The AFE was fabricated in 0.18 m CMOS; electrical characterization and multi-channel FDM results are provided, including GFET-based signal modulation and IC/DSP demodulation. Long-term, this approach can simultaneously enable high signal count, high spatial resolution, and high temporal precision to infer functional interactions between neurons while markedly decreasing access wires.

This paper presents the concept of Gastric Seed, which is an ultrasonically interrogated millimeter-sized implant for gastric electrical-wave (also known as slow waves, SWs) recording. A network of Gastric Seeds can be endoscopically implanted within the stomach submucosal space for large-scale SW recording. This paper also summarizes our recent effort towards Gastric Seed development including ultrasonic self-regulated power management and addressable ultrasonic pulse-based data transfer. The proposed power management in the form of a voltage doubler only requires a single off-chip capacitor for simultaneous rectification, regulation and over-voltage protection (OVP) by utilizing ultrasonic transducer's internal capacitance and reverse current. For data transfer, sharp ultrasonic pulses are transmitted to reduce the implant's power consumption. A proof-of-concept addressable chip was fabricated in a 0.35-μm standard CMOS process. Utilizing two pairs of millimeter-sized stacked power/data ultrasonic transducers spaced by 3.75 cm in a water tank, the chip achieved measured regulated voltage of 3 V and data rate of 75 kbps with the data transmitter energy consumption of 440 pJ/bit.

This brief presents a frequency-modulation-based analog-to-digital converter (FM ADC) that takes advantage of the coding gain resulting from bandwidth expansion in the analog domain of FM systems to achieve high dynamic range and incorporates a highly digital demodulation approach for power efficiency. The novel architecture employs a sinusoidal output voltage-controlled oscillator (VCO), a relatively low-resolution successive approximation register ADC to sample signals in the FM domain, and then a digital signal processing FM demodulator to recover high-resolution samples of the VCO's original analog input. The proposed ADC is implemented in 0.5-mm of 65-nm CMOS; it achieves 104-dB DR, 99-dB SNR, and 71-dB SNDR in a 44-kHz bandwidth while dissipating 678 W of power. The architecture of the FM ADC leverages analog domain processing for system performance and digital domain processing for lower power. This novel approach presents a viable alternative to delta-sigma converters for high dynamic range conversion in advanced process nodes.

This paper proposes a modified Eulerian Video Magnification (EVM) algorithm and a hardware implementation of a motion magnification core for smart image sensors. Compared to the original EVM algorithm, we perform the pixel-wise temporal bandpass filtering only once rather than multiple times on all scale layers, to reduce the memory and multiplier requirement for hardware implementation. A pixel stream processing architecture with pipelined blocks is proposed for the magnification core, enabling it to readily fit common image sensing components with streaming pixel output, while achieving higher performance with lower system cost. We implemented an FPGA-based prototype that is able to process up to 90M pixels per second and magnify subtle motion. The motion magnification results are comparable to the original algorithm running on PC.

An adaptive averaging low noise analog front-end (AFE) is presented for central and peripheral nerve recording applications. The proposed topology allows users to trade off, on the fly, between input referred noise and the number of channels via averaging. The new low noise amplifier (LNA) utilizes a complementary doubled input transconductance ( ) topology to effectively increase the noise efficiency factor (NEF) without chopping or use of a costly BiCMOS process. It addresses a disadvantage of the doubled- technique by a high input impedance DC-coupled LNA and saves on-chip space for higher density by eliminating AC-coupling capacitors. The proposed technique is particularly suitable for ultra-low noise multichannel recording from the peripheral nervous system (PNS) with channel selection analog multiplexer, where input signal is in tens of μV. A 32-ch proof-of-concept-prototype AFE was fabricated in a 5M2P 130-nm standard CMOS process, occupying 2.4 × 2.5 mm together with its control block. The prototype LNA consumes 11 μW from a 1 V supply, providing 3.0 μVrms input referred noise with 61 ΜΩ input impedance, which are desirable for high SNR, to be further improved by the adaptive averaging technique.

A supply-doubled pulse-shaping high voltage (HV) pulser is presented for medical ultrasound imaging applications, particularly those that use capacitive micromachined ultrasonic transducers (CMUT). The pulser employs a bootstrap circuit combined with dynamically-biased stacked transistors, which allow HV operation above process limit without lowering device reliability. The new pulser overcomes supply voltage limitation of conventional unipolar pulsers by generating output signals that are almost twice the supply level. It also can generate three-level pulses to further optimize the transmit pressure signals. A proof-of-concept prototype has been implemented in 0.18-μm HV CMOS/DMOS technology with 60 V devices. Measurement results show that the HV pulser can safely generate controllable three-level pulses with up to 85 V from 45 V supply. Acoustic measurements are conducted connecting the pulser to a CMUT with 2 pF capacitance and 8.3 MHz center frequency. The pulse shape has been adjusted for the CMUT under test to generate maximum pressure output and the results are in good agreement with a large signal CMUT model.

This brief presents a frequency-domain analysis of the latch comparator offset due to load capacitor mismatch. Although the analysis is applied to the static latch comparator, the developed method can be extended to the dynamic latch comparator.

This brief presents a monolithically integrated fully differential linear HV amplifier as the driver of an ultrasonic transducer. The linear amplifier is capable of transmitting HV arbitrary signals with a very low harmonic distortion, which is suitable for tissue harmonic imaging and other ultrasonic modes for enhanced imaging quality. The amplifier is designed and implemented using the 0.7-m CMOS silicon-on-insulator process with 120-V devices. The amplifier, when driving a load of 300 pF in parallel with 100 Ω, is capable of transmitting a sine-wave signal with a frequency of up to 4.4 MHz, a maximum signal swing of 180 V, and a second-order harmonic distortion (HD2) of -56 dBc but only dissipating an average power of 62 mW with a 0.1% duty cycle.

The Tongue Drive System (TDS) is a new unobtrusive, wireless, and wearable assistive device that allows for real-time tracking of the voluntary tongue motion in the oral space for communication, control, and navigation applications. The latest TDS prototype appears as a wireless headphone and has been tested in human subject trials. However, the robustness of the external TDS (eTDS) in real-life outdoor conditions may not meet safety regulations because of the limited mechanical stability of the headset. The intraoral TDS (iTDS), which is in the shape of a dental retainer, firmly clasps to the upper teeth and resists sensor misplacement. However, the iTDS has more restrictions on its dimensions, limiting the battery size and consequently requiring a considerable reduction in its power consumption to operate over an extended period of two days on a single charge. In this brief, we propose an ultralow-power local processor for the TDS that performs all signal processing on the transmitter side, following the sensors. Assuming the TDS user on average issuing one command/s, implementing the computational engine reduces the data volume that needs to be wirelessly transmitted to a PC or smartphone by a factor of 1500×, from 12 kb/s to ~8 b/s. The proposed design is implemented on an ultralow-power IGLOO nano field-programmable gate array (FPGA) and is tested on AGLN250 prototype board. According to our post-place-and-route results, implementing the engine on the FPGA significantly drops the required data transmission, while an application-specific integrated circuit (ASIC) implementation in a 65-nm CMOS results in a 15× power saving compared to the FPGA solution and occupies a 0.02-mm footprint. As a result, the power consumption and size of the iTDS will be significantly reduced through the use of a much smaller rechargeable battery. Moreover, the system can operate longer following every recharge, improving the iTDS usability.

A power-efficient wireless capacitor charging system for inductively powered applications has been presented. A bank of capacitors can be directly charged from an ac source by generating a current through a series charge injection capacitor and a capacitor charger circuit. The fixed charging current reduces energy loss in switches, while maximizing the charging efficiency. An adaptive capacitor tuner compensates for the resonant capacitance variations during charging to keep the amplitude of the ac input voltage at its peak. We have fabricated the capacitor charging system prototype in a 0.35-m 4-metal 2-poly standard CMOS process in 2.1 mm of chip area. It can charge four pairs of capacitors sequentially. While receiving 2.7-V peak ac input through a 2-MHz inductive link, the capacitor charging system can charge each pair of 1 F capacitors up to ±2 V in 420 s, achieving a high measured charging efficiency of 82%.

This brief presents a standalone closed-loop wireless power transmission system that is built around a commercial off-the-shelf (COTS) radio-frequency identification (RFID) reader (TRF7960) operating at 13.56 MHz. It can be used for inductively powering implantable biomedical devices in a closed loop. Any changes in the distance and misalignment between transmitter and receiver coils in near-field wireless power transmission can cause a significant change in the received power, which can cause either a malfunction or excessive heat dissipation. RFID circuits are often used in an open loop. However, their back telemetry capability can be utilized to stabilize the received voltage on the implant. Our measurements showed that the delivered power to the transponder was maintained at 11.2 mW over a range of 0.5 to 2 cm, while the transmitter power consumption changed from 78 mW to 1.1 W. The closed-loop system can also oppose voltage variations as a result of sudden changes in the load current.

We present an adaptive reconfigurable active voltage doubler (VD)/rectifier (REC) (VD/REC) in standard CMOS, which can adaptively change its topology to either a VD or a REC by sensing the output voltage, leading to more robust inductive power transmission over an extended range. Both active VD and REC modes provide much lower dropout voltage and far better power conversion efficiency (PCE) compared to their passive counterparts by adopting offset-controlled high-speed comparators that drive the rectifying switches at proper times in the high-frequency band. We have fabricated the active VD/REC in a 0.5-µm 3-metal 2-poly CMOS process, occupying 0.585 mm of chip area. In an exemplar setup, VD/REC extended the power transmission range by 33% (from 6 to 8 cm) in relative coil distance and 41.5% (from 53° to 75°) in relative coil orientation compared to using the REC alone. While providing 3.1-V dc output across a 500-Ω load from 2.15- (VD) and 3.7-V (REC) peak ac inputs at 13.56 MHz, VD/REC achieved measured PCEs of 70% and 77%, respectively.